At its core, a hardware interrupt is a signal sent to the processor by external hardware or internal system events demanding immediate attention. This mechanism bypasses the standard program counter flow, forcing the CPU to suspend its current task and execute a specific routine known as an interrupt service routine, or ISR. Unlike polling, where the processor continuously checks the status of a device, an interrupt delivers a just-in-time notification the instant an event occurs, such as a key press on a keyboard or the arrival of a network packet. This fundamental concept is the bedrock of responsive computing, allowing systems to handle asynchronous events with minimal latency and maximum efficiency.
The Mechanics of Interrupt Handling
The process of handling an interrupt is a precisely choreographed sequence executed in mere clock cycles. When an interrupt request, or IRQ, is asserted, the CPU finishes the execution of the current instruction and then enters a protected sequence known as the interrupt cycle. During this cycle, the processor saves the current program status word, which includes the program counter and processor flags, onto a dedicated stack. This preservation is critical because it allows the system to return to the exact state of execution after the interrupt service routine has completed its work. Following the context save, the hardware loads the processor with a new address, pointing to the start of the ISR, effectively transferring control to the software designed to handle that specific event.
Interrupt Controllers and Prioritization
Modern systems rarely rely on a single interrupt line; instead, they utilize sophisticated interrupt controllers to manage multiple sources. These controllers, such as the legacy Programmable Interrupt Controller (PIC) or the more advanced Advanced PIC (APIC), act as traffic cops for hardware signals. Their primary role is to prioritize interrupts, ensuring that a critical event, like a hard disk signaling data readiness, can interrupt a less critical task, such as a periodic timer tick. When multiple devices request service simultaneously, the controller evaluates their priority levels and grants access to the CPU based on a strict hierarchy, preventing lower-priority noise from disrupting high-priority operations.
Categories of Hardware Interrupts
Not all interrupts are created equal, and understanding the distinction between maskable and non-maskable interrupts is essential for system stability. A maskable interrupt (INTR) can be temporarily ignored, or masked, by setting a specific flag within the processor's status register. This allows the system to manage interrupt traffic efficiently, batching less critical requests to optimize throughput. In stark contrast, a non-maskable interrupt (NMI) is an emergency signal that cannot be ignored by the standard interrupt mask bit. NMIs are reserved for catastrophic events such as critical parity errors, hardware failures, or system lockups, where immediate intervention is required to prevent data corruption or system instability.
Edge-Triggered vs. Level-Triggered Interrupts
The physical signaling of an interrupt can occur in two primary ways: edge-triggered and level-triggered. An edge-triggered interrupt activates on a transition, such as the rising or falling edge of a voltage signal. Once the edge is detected, the request is asserted, and the CPU will service it at its earliest convenience. Level-triggered interrupts, however, remain active for the duration of the signal level. As long as the voltage level remains high or low, the interrupt line is considered active. While level-triggered interrupts are generally easier for hardware to detect and can handle missed signals, they require careful management to ensure the same interrupt condition is not serviced repeatedly, a problem known as interrupt locking.
The Impact on System Performance and Design
More perspective on Hardware interrupts can make the topic easier to follow by connecting earlier points with a few simple takeaways.
